A Data-Transfer Architecture for Fast Multi-Bit Serial Access Mode DRAM
説明
A data-transfer architecture for both fast multi-bit serial access mode and multi-output pin configuration DRAM is described in this paper. The key feature of the newly developed architecture to realize fast serial access time is the concurrent data-transfer of two cascade serial outputs in a CAS cycle using time-multiplexed data-bus. The data-transfer per one output pin is achieved by only two pairs of time-multiplexed data-bus. The data bus enables to minimize die size compared with non time-multiplexed data-bus; conventional technique. By using the architecture, a 64K × 4b nibble mode DRAM of small die size and fast nibble access time has been developed.
収録刊行物
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- ESSCIRC '85: 11th European Solid-State Circuits Conference
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ESSCIRC '85: 11th European Solid-State Circuits Conference 161-165, 1985-09-01
IEEE
