Design evaluation of injection enhancement gate transistor based on device simulation

Description

The on-state voltage and the turn-off loss were simulated for many kinds of injection enhancement gate transistors (IEGTs) with different trench-MOS channel mobilities (/spl mu//sub eff/), trench depths and thin-out ratios. It has been found that a high /spl mu//sub eff/, a deep trench and a small thin-out ratio are effective in improving the trade-off between on-state voltage and turn-off loss.

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