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Advanced CMOS Technology beyond 45nm Node
Description
At the time of CMOS device development in 45 nm node, newly developed materials and techniques have been discussed and experimented to achieve power-performance requirement. Based on the published reports, the overview of current 45 nm node technology development status is summarized. Then, the prevision of 32 nm node device design strategy is discussed considering key technologies such as stress enhancement technique, metal high-k gate stack and non-classical device scaling both for structure and temperature.
Journal
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- 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
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2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) 1-4, 2007-01-01
IEEE
