High-performance 0.5 mu m CMOS technology for logic LSIs with embedded large capacity SRAMs
説明
The optimum device design of 0.5 mu m CMOS for logic LSIs with embedded large-capacity SRAMs (static RAMs) with a 3.3 V supply voltage is proposed. In order to attain high performance with a 3.3 V supply, the p-MOSFET structure was designed and the gate oxide thickness and junction capacitance were optimized. A poly-Si load SRAM cell with a triple-well structure on p-substrate, WSi-polycide gate electrode, and triple-level metallization with W plug via holes were implemented. By careful design of each parameter and proper integration of the technologies, a high-performance 0.5 mu m CMOS with large-capacity cache memories was realized. >
収録刊行物
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- International Electron Devices Meeting 1991 [Technical Digest]
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International Electron Devices Meeting 1991 [Technical Digest] 489-492, 2002-12-09
IEEE
