Bus architecture for 600-MHz 4.5-Mb DDR SRAM
説明
A double data rate (DDR) SRAM bus architecture which can eliminate any speed penalty for doubling the I/O frequency and support single data rate (SDR) compatibility has been proposed. A method to guarantee data coherency for both DDR and SDR has also been described. With this architecture, we developed a 4.5 Mb DDR SRAM. Under the typical 2.5 V condition, a 600 MHz I/O frequency was achieved.
収録刊行物
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- 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215)
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1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215) 178-179, 2002-11-27
IEEE