Verification by error modeling : using testing techniques in hardware verification
Bibliographic Information
- Title
- "Verification by error modeling : using testing techniques in hardware verification"
- Statement of Responsibility
- by Katarzyna Radecka, Zeljko Zilic
- Publisher
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- Kluwer Academic
- Publication Year
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- c2003
- Book size
- 25 cm
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Notes
Includes bibliographical references (p. [197]-209) and index
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Details 詳細情報について
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- CRID
- 1130000796498681856
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- NII Book ID
- BA65250324
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- ISBN
- 1402076525
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- LCCN
- 2003062044
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- Web Site
- https://lccn.loc.gov/2003062044
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- Text Lang
- en
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- Country Code
- us
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- Title Language Code
- en
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- Place of Publication
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- Boston
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- Data Source
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- CiNii Books