Hierarchical modeling for VLSI circuit testing

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Bibliographic Information

Title
"Hierarchical modeling for VLSI circuit testing"
Statement of Responsibility
by Debashis Bhattacharya, John P. Hayes
Publisher
  • Kluwer Academic Publishers
Publication Year
  • c1990
Book size
24 cm

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Notes

Includes bibliographical references (p. [149]-155)

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