16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS
Journal
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- 2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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2019 IEEE International Solid- State Circuits Conference - (ISSCC) 2019-02
IEEE