16.1 A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS

収録刊行物

• 2019 IEEE International Solid- State Circuits Conference - (ISSCC)

  2019 IEEE International Solid- State Circuits Conference - (ISSCC) 2019-02

  IEEE