Electrical and Thermal Analysis of Bumpless Build Cube 3D Using Wafer-on-Wafer and Chip-on-Wafer for Near Memory Computing

  • Norio Chujo
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan
  • Hiroyuki Ryoson
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan
  • Koji Sakui
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan
  • Shinji Sugatani
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan
  • Tomoji Nakamura
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan
  • Takayuki Ohba
    Tokyo Institute of Technology, IIR, The WOW alliance,Yokohama,Japan

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