A 1.25-GS/s 7-b SAR ADC With 36.4-dB SNDR at 5 GHz Using Switch-Bootstrapping, USPC DAC and Triple-Tail Comparator in 28-nm CMOS
書誌事項
- 公開日
- 2018-07
- 権利情報
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- https://ieeexplore.ieee.org/Xplorehelp/downloads/license-information/IEEE.html
- DOI
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- 10.1109/jssc.2018.2822823
- 公開者
- Institute of Electrical and Electronics Engineers (IEEE)
この論文をさがす
収録刊行物
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- IEEE Journal of Solid-State Circuits
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IEEE Journal of Solid-State Circuits 53 (7), 1889-1901, 2018-07
Institute of Electrical and Electronics Engineers (IEEE)
