Patterning of silicon nitride for CMOS gate spacer technology. III. Investigation of synchronously pulsed CH3F/O2/He plasmas

<jats:p>Si3N4 spacer etching processes are one of the most critical steps of transistor fabrication technologies since they must be at the same time very anisotropic to generate straight spacer profiles and extremely selective to silicon in order to minimize the silicon consumption in source/drain regions. Minimizing the silicon recess and ion-induced damages to silicon surfaces are key criterions for fully depleted silicon on insulator technologies in order to ensure a high surface quality for the subsequent step of silicon epitaxy. In this work, the authors investigate synchronously pulsed CH3F/O2/He plasmas for the etching of Si3N4 spacers selectively toward Si (the selectivity typically relies on the oxidation of the silicon layer). First, they compare the Si3N4 and silicon etch rates measured in continuous wave (CW) plasmas, while varying the [CH3F]/[O2] ratio, to the etch rates measured using pulsed plasmas. Using angle resolved x-ray photoelectron spectroscopy and scanning transmission electron microscopy (STEM) cross sections, they show that the silicon thickness oxidized during the Si3N4 etching decreases from 1.5 nm in CW to 0.5 using a plasma pulsed at 1 kHz and 10% duty cycle, and the percentage of carbon implanted into the silicon substrate is reduced by a factor 2 using pulsed plasma conditions. Moreover, STEM cross sections show an improvement of the spacer profile when the plasma is pulsed at 1 kHz and low duty cycles, with a rounded spacer top leading to a better gate encapsulation, instead of the faceted spacer obtained using CW plasma conditions.</jats:p>