Review of methods for the mitigation of plasma‐induced damage to low‐dielectric‐constant interlayer dielectrics used for semiconductor logic device interconnects
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- Hideshi Miyajima
- Advanced Memory Development Center Toshiba Memory Corporation, Yamanoisshiki‐cho Yokkaichi Japan
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- Kenji Ishikawa
- Graduate School of Engineering Nagoya University, Furo‐cho Chikusa Nagoya Japan
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- Makoto Sekine
- Graduate School of Engineering Nagoya University, Furo‐cho Chikusa Nagoya Japan
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- Masaru Hori
- Graduate School of Engineering Nagoya University, Furo‐cho Chikusa Nagoya Japan
説明
<jats:title>Abstract</jats:title><jats:p>The developments in advanced interconnect technology for semiconductor logic devices for the mitigation of plasma‐induced damage to low‐dielectric‐constant (low‐k) materials, including fluorosilicate glass and carbon‐doped silicon oxide is reviewed. The chemical bond structures of low‐k materials are summarized to help mitigate the k value degradation caused by moisture uptake after plasma processes. Damage suppression is accomplished by integrating deposition chemistries, pattern etch transfer, and post‐etch cleaning technologies. On the basis of analyses results, a discussion on the bond engineering of low‐k materials and their degradation during plasma processing is given. Challenges facing low‐k interconnect technology are also addressed.</jats:p>
収録刊行物
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- Plasma Processes and Polymers
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Plasma Processes and Polymers 16 (9), 2019-06-27
Wiley
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詳細情報 詳細情報について
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- CRID
- 1361131414748954880
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- ISSN
- 16128869
- 16128850
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- データソース種別
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- Crossref
- KAKEN
