A 265-$\mu$ W Fractional-${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS
収録刊行物
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- IEEE Journal of Solid-State Circuits
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IEEE Journal of Solid-State Circuits 54 (12), 3478-3492, 2019-12
Institute of Electrical and Electronics Engineers (IEEE)