Reducing damage to Si substrates during gate etching processes by synchronous plasma pulsing
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- Camille Petit-Etienne
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Maxime Darnon
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Laurent Vallier
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Erwine Pargon
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Gilles Cunge
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- François Boulard
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Olivier Joubert
- CNRS-LTM , 17, rue des martyrs, 38054 Grenoble Cedex, France
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- Samer Banna
- Applied Materials Inc. , 974E Arques Ave., Sunnyvale, California 95085
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- Thorsten Lill
- Applied Materials Inc. , 974E Arques Ave., Sunnyvale, California 95085
説明
<jats:p>Plasma oxidation of the c-Si substrate through a very thin gate oxide layer can be observed during HBr/O2/Ar based plasma overetch steps of gate etch processes. This phenomenon generates the so-called silicon recess in the channel and source/drain regions of the transistors. In this work, the authors compare the silicon recess generated by continuous wave HBr/O2/Ar plasmas and synchronous pulsed HBr/O2/Ar plasmas. Thin SiO2 layers are exposed to continuous and pulsed HBr/O2/Ar plasmas, reproducing the overetch process conditions of a typical gate etch process. Using in situ ellipsometry and angle resolved X-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess can be reduced from 4 to 0.8 nm by pulsing the plasma in synchronous mode.</jats:p>
収録刊行物
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- Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena
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Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena 28 (5), 926-934, 2010-08-27
American Vacuum Society