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- Chonan Yasunori
- Department of Electronics and Information Systems, Factory of System Science and Technology, Akita Prefectual University
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- Komiyama Takao
- Department of Electronics and Information Systems, Factory of System Science and Technology, Akita Prefectual University
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- Onuki Jin
- Department of Materials Science and Engineering Ibaraki University
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- Nagano Takahiro
- Intellexres Laboratory
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- Akahoshi Haruo
- Hitachi Research Laboratory
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- Itabashi Takeyuki
- Advanced Research Laboratory, Hitachi Ltd.
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- Saito Tatuyuki
- Hitachi, Ltd.
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- Khoo Khyoupin
- Department of Materials Science and Engineering Ibaraki University
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抄録
Copper electroplating has been used for making interconnections in large-scale integration (LSI). Sub-100-nm-wide, deep trenches with aspect-ratios over 6 were fully filled by optimizing DC and pulse electroplating processes. Grain sizes of Cu of sub-100-nm wide trenches after electroplating were 70 nm for DC electroplating and 58 nm for pulse electroplating. The Cu grain sizes of Cu interconnects by DC plating after electroplating increased with the annealing temperature.
収録刊行物
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- MATERIALS TRANSACTIONS
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MATERIALS TRANSACTIONS 47 (5), 1417-1419, 2006
公益社団法人 日本金属学会
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詳細情報 詳細情報について
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- CRID
- 1390001204251149440
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- NII論文ID
- 10017490545
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- NII書誌ID
- AA1151294X
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- ISSN
- 13475320
- 13459678
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- NDL書誌ID
- 7915081
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可
