Development of high-efficient CMP process of SiC wafers for power electronics

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  • パワーエレクトロニクス用SiCウェーハの高能率CMPプロセスの開発
  • パワーエレクトロニクスヨウ SiC ウェーハ ノ コウノウリツ CMP プロセス ノ カイハツ

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Abstract

Silicon carbide (SiC) is an important semiconductor material for high power electronic applications. However, it is difficult to obtain effective removal rates with chemical mechanical polishing (CMP) of SiC due to its high hardness and strong chemical inertness. In this study, we investigated a high-efficiency CMP process using a high-rotational CMP machine with strong oxidizer slurry. The results showed that it is possible to achieve a high removal rate > 10 μm/h on Si-face (0001) 4H-SiC. Then, we compared the surface quality with that obtained by conventional colloidal silica-based slurry. We examined the usefulness of the two-step CMP process achieving SiC epi-ready surface in a short time, using confocal optical microscopy with differential interference contrast (CDIOM), atomic force microscopy (AFM), and mirror electron microscope (MEM).

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