Towards Ultra-High-Speed Cryogenic Single-Flux-Quantum Computing

DOI Web Site 被引用文献8件 参考文献26件 オープンアクセス
  • ISHIDA Koki
    Graduate School of Information Science and Electrical Engineering, Kyushu University
  • TANAKA Masamitsu
    Department of Electronics, Nagoya University
  • ONO Takatsugu
    Faculty of Information Science and Electrical Engineering, Kyushu University
  • INOUE Koji
    Faculty of Information Science and Electrical Engineering, Kyushu University

書誌事項

公開日
2018-05-01
DOI
  • 10.1587/transele.e101.c.359
公開者
一般社団法人 電子情報通信学会

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説明

<p>CMOS microprocessors are limited in their capacity for clock speed improvement because of increasing computing power, i.e., they face a power-wall problem. Single-flux-quantum (SFQ) circuits offer a solution with their ultra-fast-speed and ultra-low-power natures. This paper introduces our contributions towards ultra-high-speed cryogenic SFQ computing. The first step is to design SFQ microprocessors. From qualitatively and quantitatively evaluating past-designed SFQ microprocessors, we have found that revisiting the architecture of SFQ microprocessors and on-chip caches is the first critical challenge. On the basis of cross-layer discussions and analysis, we came to the conclusion that a bit-parallel gate-level pipeline architecture is the best solution for SFQ designs. This paper summarizes our current research results targeting SFQ microprocessors and on-chip cache architectures.</p>

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