A Hybrid CMOS/CCD ISAS (Image Signal Accumulation Sensor) : Technical Feasibility

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A new ultra-high-speed image sensor "Hybrid CMOS/CCD ISAS" is presented. ISAS stands for "Image Signal Accumulation Sensor". A folded CCD is installed in each pixel, which serves as an in-situ memory for parallel recording at all pixels. The CCD is looped so that image signals captured at plural of capturing operations are automatically accumulated on the memory CCD. A CMOS readout circuitry is also installed in the pixel for fast and flexible signal readout. By directly reading out signals through the CMOS readout circuit without recording them in the in-pixel CCD memory, the sensor works as a conventional parallel and partial readout high-speed imager as well. A set of Z-shaped electrodes is proposed to fold the CCD and fabricate it with a standard CMOS process. Therefore, the sensor can be fabricated solely with a CIS process. Technical feasibility of the sensor is confirmed through simulations.

Journal

  • ITE Technical Report

    ITE Technical Report 35.19 (0), 9-12, 2011

    The Institute of Image Information and Television Engineers

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