Development of Low-Cost and Highly Reliable Wafer Process Package "WPP-2".
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- KAZAMA Atsushi
- Mechanical Engineering Research Laboratory, Hitachi, Ltd.
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- SATOH Toshiya
- Hitachi Research Laboratory, Hitachi, Ltd.
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- YAMAGUCHI Yoshihide
- Production Engineering Research Laboratory, Hitachi, Ltd.
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- ANJOH Ichiro
- Semiconductor and Integrated Circuits, Hitachi, Ltd.
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- NISHIMURA Asao
- Semiconductor and Integrated Circuits, Hitachi, Ltd.
Bibliographic Information
- Other Title
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- 低コスト・高信頼ウエハプロセスパッケージ“WPP‐2”の開発
- テイコスト コウシンライ ウエハプロセスパッケージ WPP 2 ノ カイハツ
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Abstract
A new wafer-level chip-size-package, which realizes high reliability at low cost, has been developed. The package contains a stress-relaxation layer, so it can achieve a lifetime of over 1000 cycles under a -55/125°C temperature cycling test for its solder joints, even when the package contains a large chip of about 100mm2 and is mounted on a FR-4 motherboard without an underfill assembly. To realize such reliability above, the stress-relaxation layer was optimized, by using finite element analysis, to have a thickness of 75μm and a Young's modulus of 1000 MPa. The stress-relaxation layer is formed by printing to lower the cost of manufacturing the package. The high reliability of the designed package was confirmed experimentally. Under temperature cycling test, none of 50 test samples failed even after 1400 cycles, and the lifetime to 50% failure for the samples was more than 3000 cycles.
Journal
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- Journal of The Japan Institute of Electronics Packaging
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Journal of The Japan Institute of Electronics Packaging 5 (3), 264-271, 2002
The Japan Institute of Electronics Packaging
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Keywords
Details 詳細情報について
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- CRID
- 1390001204560868480
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- NII Article ID
- 130004165952
- 110001716476
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- NII Book ID
- AA11231565
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- ISSN
- 1884121X
- 13439677
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- NDL BIB ID
- 6156258
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- Text Lang
- ja
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- Data Source
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- JaLC
- NDL
- Crossref
- CiNii Articles
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- Abstract License Flag
- Disallowed