Feasibilities on Microthin Underfill Technologies for Gap Less than 10.MU.m Applied to Flip-Chip Bonding in 20.MU.m Pitch.

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  • TOMITA Yoshihiro
    Tsukuba Research Center, Electronics System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET)
  • ANDO Tatsuya
    Tsukuba Research Center, Electronics System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET)
  • TANAKA Naotaka
    Tsukuba Research Center, Electronics System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET)
  • SATO Tomotoshi
    Tsukuba Research Center, Electronics System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET)
  • TAKAHASHI Kenji
    Tsukuba Research Center, Electronics System Integration Technology Research Department, Association of Super-Advanced Electronics Technologies (ASET)

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Other Title
  • ２０μｍピッチフリップチップにおける１０μｍ以下の微細間隙アンダーフィルに関する基礎検証
  • 20マイクロm ピッチフリップチップ ニ オケル 10マイクロm イカ ノ ビサイ カンゲキ アンダーフィル ニ カンスル キソ ケンショウ

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Abstract

The underfill process was examined to encapsulate the gaps less than 10μm in thickness between the 10-mm-square silicon chips and the interposer connected with 12μm bumps in 20μm pitch. The analysis by the finite element method (FEM) found that the filler particles in epoxy resin were necessary for the relaxation of the thermal stress on the top surface of the 50-μm-thickness thin silicon chip at the decrease of temperature, because the fillers could reduce the thermal stress contraction of the underfill resin. Then, the diameter of the filler particles incorporated in epoxy resin at 50% in weight was optimized as the 0.3pm in average and 0.35μm in maximum for the 3μm gap in thickness. As the results of the experiment on the encapsulation, it was confirmed that the optimum filler-dispersion could realize the underfill encapsulation for 20-μm-pitch flip-chip interconnections leading to the die-stacked 3D LSI.

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