Ni-Salicided Poly-Si/poly-SiGe-Layered Gate Technology for 65-nm-node CMOSFETs

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  • Muto Akiyoshi
    Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
  • Ohji Hiroshi
    Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
  • Maeda Takeshi
    Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
  • Torii Kazuyoshi
    Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)
  • Kitajima Hiroshi
    Research Department 1, Semiconductor Leading Edge Technologies, Inc. (SELETE)

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説明

A poly-Si/poly-SiGe-layered gate electrode with a high Ge content that is suitable for Ni silicidation has been examined. The optimum Ge content for suppressing gate depletion was found to be 30%. It was found that the in situ deposition of a thin Si layer after SiGe deposition was effective in suppressing void formation. A smooth Si0.7Ge0.3 film without voids was obtained as either polycrystalline or amorphous. The enhancement of boron activation in poly-Si0.7Ge0.3 was confirmed while gate depletion became large for α-Si0.7Ge0.3 because of its lower boron diffusivity. Stable Ni silicidation over the 300 mm wafers was achieved by using a poly-Si/poly-Si0.7Ge0.3-layered gate electrode.

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