A High-Throughput Binary Arithmetic Coding Architecture for H.264/AVC CABAC

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  • LIU Yizhong
    Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University
  • SONG Tian
    Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University
  • SHIMAMOTO Takashi
    Computer Systems Engineering, Institute of Technology and Science, Graduate School of Engineering, Tokushima University

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In this paper, we propose a high-throughput binary arithmetic coding architecture for CABAC (Context Adaptive Binary Arithmetic Coding) which is one of the entropy coding tools used in the H.264/AVC main and high profiles. The full CABAC encoding functions, including binarization, context model selection, arithmetic encoding and bits generation, are implemented in this proposal. The binarization and context model selection are implemented in a proposed binarizer, in which a FIFO is used to pack the binarization results and output 4 bins in one clock. The arithmetic encoding and bits generation are implemented in a four-stage pipeline with the encoding ability of 4 bins/clock. In order to improve the processing speed, the context variables access and update for 4 bins are paralleled and the pipeline path is balanced. Also, because of the outstanding bits issue, a bits packing and generation strategy for 4 bins paralleled processing is proposed. After implemented in verilog-HDL and synthesized with Synopsys Design Compiler using 90nm libraries, this proposal can work at the clock frequency of 250MHz and takes up about 58K standard cells, 3.2Kbits register files and 27.6K bits ROM. The throughput of processing 1000M bins per second can be achieved in this proposal for the HDTV applications.

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