A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS

DOI Web Site BIBCODE 参考文献31件
  • HE Xun
    Graduate School of Information, Production and Systems, Waseda University
  • JIN Xin
    Information Technology Research Organization, Waseda University
  • WANG Minghui
    Graduate School of Information, Production and Systems, Waseda University
  • ZHOU Dajiang
    Graduate School of Information, Production and Systems, Waseda University
  • GOTO Satoshi
    Graduate School of Information, Production and Systems, Waseda University

書誌事項

公開日
2011
DOI
  • 10.1587/transfun.e94.a.2609
公開者
一般社団法人 電子情報通信学会

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説明

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. The SIMD cores support 8/16bits SIMD MAC instructions, and vertical vector access. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. This hierarchical network can provide more than 192GB/s low latency inter-core BW in average. The 4-ports L2 cache architecture is also designed to provide 192GB/s L2 cache BW. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Compared with MOESI, 67.8% of L1 cache energy can be saved in 32 cores case. The whole system including 32 vector cores, 256KB L2 cache, 64-bit DDRII PHY and two PLL units, occupy 25mm2 in 65nm CMOS. It can achieve a peak performance of 375 GMACs and 98 GMACs/W at 1.2V.

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