Study on Planarization of Silicon-Wafer by CMP.

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  • ＣＭＰによるシリコンウェハの平坦化に関する研究
  • CMP ニ ヨル シリコンウェハ ノ ヘイタンカ ニ カンスル ケンキュウ

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In order to make a highly integrated LSI, the circuits of patterned metal layers are constructed on a semiconductor-wafer as three-dimensional structure. In the processes of constructing three-dimensional circuits, the dielectric films that should be planarity before depositing patterned metal layers on it are made between the circuit layers. CMP (Chemical Mechanical Polish) is the most effective technology for planarizing semiconductor-wafer surfaces. For improving the functions and performance of a CMP machine, the various items such as polishing pressure, polishing pad, retainer ring, backing film and ingredients of slurry have to be taken into consideration. More efficient processing conditions for CMP and machine parameters to be designed are decided by know-how and knowledge obtained by repeating basic experiments. However, since it takes much time and manpower to get them via experiments, it is required to determine by computer analyses. Since pressure applied on a semiconductor-wafer surface is the most essential factor about the rate of mechanical polish, it is indispensable to obtain pressure distribution on the wafer-surface in order to estimate the rate. In this paper, pressure distribution given to the wafer-surface is computed by FEM (Finite Element Method) to estimate the polishing rate in order to determine optimum machine parameters to be design.

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