A New Method of Component-Level ESD Test to Assess System-Level ESD Risk for Ics

DOI

抄録

As components or products become more reliable, the failure by electro static discharge (ESD) is getting one of the most important problems. In the past, ESD was recognized as a system-level problem, but it has recently been recognized as a component-level problem such as dynamic random access memory (DRAM) and solid state drive (SSD). It is difficult to assess the system-level ESD risk for the components being developed. In this paper, component-level ESD test method is developed using transmission line pulse (TLP) to assess ESD immunity of IC products. In addition, it is verified that ESD immunity of ICs correlated with ESD immunity in system-level. Therefore, system-level ESD performance for the components being developed can be predicted using the new component-level ESD test method. This results in reduced development costs for both system and components.

収録刊行物

  • IEICE Proceeding Series

    IEICE Proceeding Series 58 ThuPM2D.2-, 2016-10-05

    The Institute of Electronics, Information and Communication Engineers

キーワード

詳細情報 詳細情報について

  • CRID
    1390003825197270016
  • NII論文ID
    230000011774
  • DOI
    10.34385/proc.58.thupm2d.2
  • ISSN
    21885079
  • 本文言語コード
    en
  • データソース種別
    • JaLC
    • CiNii Articles
  • 抄録ライセンスフラグ
    使用不可

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