A 6T-3M SOT-MRAM for in-memory computing with reconfigurable arithmetic operations

DOI Web Site 参考文献32件
  • Jin Xing
    School of Electronics and Information Technology, Sun Yat-sen University
  • Yin Ningyuan
    School of Microelectronics Science and Technology, Sun Yat-sen University
  • Chen Weichong
    School of Microelectronics Science and Technology, Sun Yat-sen University
  • Li Ximing
    School of Electronics and Information Technology, Sun Yat-sen University
  • Zhao Guihua
    School of Electronics and Information Technology, Sun Yat-sen University
  • Yu Zhiyi
    School of Microelectronics Science and Technology, Sun Yat-sen University Guangdong Provincial Key Laboratory of Optoelectronic Information Processing Chips and Systems, Sun Yat-sen University

抄録

<p>Traditional von Neumann architecture bottlenecks such as the “memory wall” limit artificial intelligence (AI) development, and in-memory computing (IMC) as a new computing architecture can solve the above problems. Spin-orbit-torque-magnetic random access memory (SOT-MRAM) has very good advantages in IMC architecture because of its good compatibility with CMOS, high tunneling magnetoresistance (TMR) ratio, and high energy efficiency. In this paper, we propose a 6T-3M-based MRAM-IMC architecture with reconfigurable memory mode and logical operation mode. The functionality of the proposed architecture is validated using the 28 nm process design kit and the SOT-MTJ model.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 20 (11), 20230152-20230152, 2023-06-10

    一般社団法人 電子情報通信学会

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