Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

DOI Web Site BIBCODE 被引用文献3件 参考文献13件
  • TAKAGI Kazuyoshi
    Department of Information Engineering, Nagoya University CREST-JST
  • ITO Yuki
    Department of Information Engineering, Nagoya University CREST-JST
  • TAKESHIMA Shota
    Department of Information Engineering, Nagoya University CREST-JST
  • TANAKA Masamitsu
    Department of Information Engineering, Nagoya University CREST-JST
  • TAKAGI Naofumi
    Department of Communications and Computer Engineering, Kyoto University CREST-JST

書誌事項

公開日
2011
DOI
  • 10.1587/transele.e94.c.288
公開者
一般社団法人 電子情報通信学会

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説明

In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

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