A Built-in Test Circuit for Electrical Interconnect Testing of Open Defects in Assembled PCBs
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- Widiant
- Institute of Technology and Science, Tokushima University
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- HASHIZUME Masaki
- Institute of Technology and Science, Tokushima University
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- SUENAGA Shohei
- Institute of Technology and Science, Tokushima University
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- YOTSUYANAGI Hiroyuki
- Institute of Technology and Science, Tokushima University
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- ONO Akira
- Kagawa National College of Technology
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- LU Shyue-Kung
- National Taiwan University of Science and Technology
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- ROTH Zvi
- Florida Atlantic University
抄録
<p>In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.</p>
収録刊行物
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E99.D (11), 2723-2733, 2016
一般社団法人 電子情報通信学会
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詳細情報 詳細情報について
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- CRID
- 1390282679355793792
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- NII論文ID
- 130005268125
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- ISSN
- 17451361
- 09168532
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- 本文言語コード
- en
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- データソース種別
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- JaLC
- Crossref
- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可