Process compensation techniques for low-voltage CMOS digital circuits

DOI Web Site 13 References
  • TSUGITA Yusuke
    Graduate School of Information Science and Technology, Hokkaido University
  • UENO Ken
    Graduate School of Information Science and Technology, Hokkaido University
  • HIROSE Tetsuya
    Department of Electrical and Electronics Engineering, Kobe University
  • ASAI Tetsuya
    Graduate School of Information Science and Technology, Hokkaido University
  • AMEMIYA Yoshihito
    Graduate School of Information Science and Technology, Hokkaido University

Bibliographic Information

Other Title
  • 低電圧CMOSディジタル回路の特性バラツキ補償技術の構築(アナログ,アナデジ混載,RF及びセンサインタフェース回路)
  • 低電圧CMOSディジタル回路の特性バラツキ補償技術の構築
  • テイデンアツ CMOS ディジタル カイロ ノ トクセイ バラツキ ホショウ ギジュツ ノ コウチク

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Abstract

In low-voltage CMOS digital circuits, threshold voltage varaition fluctuates circuit performance significantly. In this work, on-chip process compensation techniques for low-voltage CMOS digital circuits were proposed. We employed on-current compensation tehchniques in a digital circuit by using a reference current, that is independent of process variations. In addition, the technique can be applied to circuit performance's fluctuation induced by temperature change. We confirmed the operation of the circuit by a SPICE simulation with a set of 0.35-μm standard CMOS parameters, and performed Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs. SPICE simulation demonstrated that the process variations of digital circuits were improved to 65% by applying the proposed architecture. The techniques will be useful for on-chip process compensation of digital circuits.

Journal

  • ITE Technical Report

    ITE Technical Report 32.45 (0), 49-54, 2008

    The Institute of Image Information and Television Engineers

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