The performance evaluation of fully depleted SOI pixel detector with backgate surface potential pinning
-
- KAMEHAMA Hiroki
- Research Institute of Electronics, Shizuoka University
-
- SHRESTHA Sumeet
- Research Institute of Electronics, Shizuoka University
-
- YASUTOMI Keita
- Research Institute of Electronics, Shizuoka University
-
- KAGAWA Keiichiro
- Research Institute of Electronics, Shizuoka University
-
- TAKEDA Ayaki
- Department of Physics, Kyoto University
-
- TSURU Takeshi
- Department of Physics, Kyoto University
-
- ARAI Yasuo
- KEK, National High Energy Accelerator Research Organization
-
- KAWAHITO Shoji
- Research Institute of Electronics, Shizuoka University
Bibliographic Information
- Other Title
-
- バックゲート表面電位固定構造を用いた完全空乏化SOIピクセル検出器の性能評価(イメージセンサおよび一般,2015 IISWとVLSIシンポジウムからの発表報告)
- バックゲート表面電位固定構造を用いた完全空乏化SOIピクセル検出器の性能評価
- バックゲート ヒョウメン デンイ コテイ コウゾウ オ モチイタ カンゼン クウボウカ SOI ピクセル ケンシュツキ ノ セイノウ ヒョウカ
Search this article
Abstract
A novel SOI (Silicon-On-Insulator) pixel photo detector with full depletion and backgate surface potential pinning is proposed in this presentation. The detector greatly increases charge-to-voltage conversion gain while stabilizing the operation of SOI circuits. Low noise and wide dynamic range operations are attained. A double doping technique increasing potential barrier to holes at the surface region is effective for a stable operation to the variation of back bias voltage. The structure of the pixel detector, simulation results of potential distributions and measurement results are reported.
Journal
-
- ITE Technical Report
-
ITE Technical Report 39.35 (0), 37-40, 2015
The Institute of Image Information and Television Engineers
- Tweet
Details 詳細情報について
-
- CRID
- 1390282679505162240
-
- NII Article ID
- 110009990381
-
- NII Book ID
- AN1059086X
-
- ISSN
- 24241970
- 13426893
-
- NDL BIB ID
- 026775279
-
- Text Lang
- ja
-
- Data Source
-
- JaLC
- NDL
- CiNii Articles
-
- Abstract License Flag
- Disallowed