Impact of Device Degradation Due to NBTI on Gated Clock Systems

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  • ゲーテドクロックシステムへのNBTI起因デバイス劣化のインパクト
  • ゲーテドクロック システム エ ノ NBTI キイン デバイス レッカ ノ インパクト

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Abstract

On the system with gated clock, NBTI causes the unbalanced degradation in the threshold voltage of PMOSFETs. In this paper, we clarify the impact of NBTI degradation on timing characteristics such as setup time, hold time and clock skew. We demonstrate that the maximum operating frequency regarding setup time violation becomes worse, hold time constraint becomes better, and clock skew after a gated clock cell operates better with stopped time.

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