書誌事項
- タイトル別名
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- Design Technology of Stacked Type Chain PRAM
- セキソウ ホウシキ Chain コウゾウ PRAM ノ セッケイホウ
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抄録
A stacked type chain PRAM which enables to realize lower cost than flash memory has been proposed. The newly proposed memory cell is consisted with a PCM for data storage and a MOS transistor connected in parallel. This memory cell is connected in series for realizing the chain structure. Cell structure, the design method for realizing stable read and write operation, and core circuit for the stacked type chain PRAM have been described. Newly proposed memory cell has been designed to adopt BiCS (Bit Cost Scalable) process technology for realizing low-cost memory. The design of the resistance of PCM and the pass transistor is key issue for realizing stable operation. For designing the row decoder, the circuit concept of the stacked FeRAM with the NAND structure cell has been successfully adopted with SGT. The newly proposed stacked type chain PRAM is a promising candidate for realizing high-speed and low-power future non-volatile semiconductor memory.
収録刊行物
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- 電気学会論文誌Ｃ（電子・情報・システム部門誌）
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電気学会論文誌Ｃ（電子・情報・システム部門誌） 133 (5), 937-946, 2013
一般社団法人 電気学会
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詳細情報 詳細情報について
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- CRID
- 1390282679585451008
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- NII論文ID
- 10031166973
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- NII書誌ID
- AN10065950
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- ISSN
- 13488155
- 03854221
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- NDL書誌ID
- 024670143
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- 本文言語コード
- ja
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- データソース種別
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- JaLC
- NDL
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- CiNii Articles
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- 抄録ライセンスフラグ
- 使用不可