C33 Improvement of global flatness and site flatness near wafer edge in polishing of silicon wafer
-
- SATAKE Urara
- Osaka University
-
- ENOMOTO Toshiyuki
- Osaka University
-
- HIROSE Kenji
- Osaka University
-
- FUJI Keitaro
- Osaka University
Bibliographic Information
- Other Title
-
- C33 シリコンウェーハ研磨加工におけるグローバルフラットネスとエッジサイトフラットネス(OS10 研磨技術(2))
Abstract
For increasing the integration density of semiconductor devices, there is growing demand for achieving high global flatness and site flatness especially near the wafer edge in polishing of silicon wafers. In this study, polishing conditions in double-sided polishing process were optimized to uniform material removal distribution on wafer and polishing pad properties for decreasing edge roll off were investigated.
Journal
-
- The Proceedings of The Manufacturing & Machine Tool Conference
-
The Proceedings of The Manufacturing & Machine Tool Conference 2014.10 (0), 181-182, 2014
The Japan Society of Mechanical Engineers
- Tweet
Keywords
Details 詳細情報について
-
- CRID
- 1390282680877713536
-
- NII Article ID
- 110009939355
-
- ISSN
- 24243094
-
- Text Lang
- ja
-
- Data Source
-
- JaLC
- Crossref
- CiNii Articles
-
- Abstract License Flag
- Disallowed