An Energy-Efficient Patchable Accelerator and Its Design Methods
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- YOSHIDA Hiroaki
- Fujitsu Laboratories of America
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- WAKIZAKA Masayuki
- Graduate School of Ritsumeikan University
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- YAMASHITA Shigeru
- Graduate School of Ritsumeikan University
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- FUJITA Masahiro
- VLSI Design and Education Center, The University of Tokyo
Abstract
With the shorter time-to-market and the rising cost in SoC development, the demand for post-silicon programmability has been increasing. Recently, programmable accelerators have attracted more attention as an enabling solution for post-silicon engineering change. However, programmable accelerators suffers from 5∼10X less energy efficiency than fixed-function accelerators mainly due to their extensive use of memories. This paper proposes a highly energy-efficient accelerator which enables post-silicon engineering change by a control patching mechanism. Then, we propose a patch compilation method from a given pair of an original design and a modified design. We also propose a design method to add redundant wires in advance to decrease the necessary amount of patch memory for post-silicon engineering change. Experimental results demonstrate that the proposed accelerators offer high energy efficiency competitive to fixed-function accelerators and can achieve about 5X higher efficiency than the existing programmable accelerators. We also show the trade-off between redundant wires and the necessary amount of patch memory.
Journal
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- IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E97.A (12), 2507-2517, 2014
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1390282681287066752
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- NII Article ID
- 130004706414
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- ISSN
- 17451337
- 09168508
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed