An approach to an analog CMOS spiking neural network integrated circuit development

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  • UENOHARA Seiji
    東京大学生産技術研究所　BMAI 社会連携研究部門

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  • アナログCMOSスパイキングニューラルネットワーク集積回路開発への取り組み
  • アナログ CMOS スパイキングニューラルネットワーク シュウセキ カイロ カイハツ エ ノ トリクミ

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Abstract

<p>In recent years, an integrated circuit （IC） chip development for an artificial neural network （ANN） is accelerated. Power consumption for a multiply-accumulate operation of an analog ANN chip is lower than that of a digital ANN. However, the analog ANN strongly influenced by the process variations. In order to confirm whether that an analog ANN chip without compensation can on-chip learning in real time, I have been developing an ultra-low power analog CMOS spiking neural network LSI chip. In this report, I show circuit simulation results of its synapse circuit.</p>

Journal

  • SEISAN KENKYU

    SEISAN KENKYU 70 (3), 171-174, 2018-05-01

    Institute of Industrial Science The University of Tokyo

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