Multi-column parallel QC-LDPC decoder architecture for NAND flash memory

DOI Web Site 参考文献9件
  • Shen Wei
    School of Electrical Science and Engineering, Nanjing University
  • Chen Cheng
    Microelectronics R&D Institute, ZTE Corporation
  • Sha Jin
    Shenzhen Research Institute, Nanjing University

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説明

<p>Quasi-cyclic (QC) low-density parity-check (LDPC) codes are famous for their excellent error correction performance and hardware friendly structure in NAND flash memory application. Array LDPC code is a type of highly structured QC-LDPC code that provides a good balance between performance and complexity. In this paper, a method is proposed for the construction of (18900, 17010) LDPC code that is based on the Latin square and an improved array dispersion strategy to achieve multi-column alignment of the structure. Compared with traditional design, the parallel hardware architecture reduces the number of barrel shifters by 32%. The corresponding ASIC implementation results show that the throughput of the proposed QC-LDPC code was up to 3.49 Gb/s and the throughput-to-area (TAR) of the proposed codes was significantly improved.</p>

収録刊行物

  • IEICE Electronics Express

    IEICE Electronics Express 15 (10), 20180397-20180397, 2018

    一般社団法人 電子情報通信学会

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