A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs
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- ASHIKIN Fara
- Tokushima University Universiti Teknikal Malaysia Melaka
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- HASHIZUME Masaki
- Tokushima University
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- YOTSUYANAGI Hiroyuki
- Tokushima University
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- LU Shyue-Kung
- National Taiwan University of Science and Technology
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- ROTH Zvi
- Florida Atlantic University
Abstract
<p>A design-for-testability method and an electrical interconnect test method are proposed to detect open defects occurring at interconnects among dies and input/output pins in 3D stacked ICs. As part of the design method, an nMOS and a diode are added to each input interconnect. The test method is based on measuring the quiescent current that is made to flow through an interconnect to be tested. The testability is examined both by SPICE simulation and by experimentation. The test method enabled the detection of open defects occurring at the newly designed interconnects of dies at experiments test speed of 1MHz. The simulation results reveal that an open defect generating additional delay of 279psec is detectable by the test method at a test speed of 200MHz beside of open defects that generate no logical errors.</p>
Journal
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- IEICE Transactions on Information and Systems
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IEICE Transactions on Information and Systems E101.D (8), 2053-2063, 2018-08-01
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1390845712979360256
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- NII Article ID
- 130007429462
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- ISSN
- 17451361
- 09168532
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- Text Lang
- en
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- Data Source
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- JaLC
- Crossref
- CiNii Articles
- KAKEN
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- Abstract License Flag
- Disallowed
