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Survey of the testing for 3D-VLSI
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- Takahashi Hiroshi
- Ehime Univ.
Bibliographic Information
- Other Title
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- 3次元VLSIの故障検査法に関するサーベイ
Description
Recently, the research of a testing for 3D-VLSI is one of the hottopics in the international conference of VLS testing such asInternational Test Conference, VLSI Test Symposium, Asia TestSymposium, European Test Symposium. However, the technique of thetesting 3D-VLSI has not been established yet. In this presentation, wesurvey the testing for 3D-VLSI. First, we discuss the feasibility ofthe existing design for testability techniques (Boundary scanstandard, IEEE Std 1500) to apply the testing for 3D-VLSI. Next, wepoint out the issue of the testing for TSV in 3D-VLSI. Finally, weintroduce the test generation method for the faults at the TSVs.
Journal
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- Proceedings of JIEP Annual Meeting
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Proceedings of JIEP Annual Meeting 28 (0), 231-234, 2014
The Japan Institute of Electronics Packaging
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Details 詳細情報について
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- CRID
- 1390845712979512192
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- NII Article ID
- 130007429048
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- Text Lang
- ja
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- Data Source
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- JaLC
- CiNii Articles
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- Abstract License Flag
- Disallowed