Survey of  the testing for 3D-VLSI

Takahashi Hiroshi

doi:10.11486/ejisso.28.0_231

Bibliographic Information

Other Title

３次元VLSIの故障検査法に関するサーベイ

Description

Recently, the research of a testing for 3D-VLSI is one of the hottopics in the international conference of VLS testing such asInternational Test Conference, VLSI Test Symposium, Asia TestSymposium, European Test Symposium. However, the technique of thetesting 3D-VLSI has not been established yet. In this presentation, wesurvey the testing for 3D-VLSI. First, we discuss the feasibility ofthe existing design for testability techniques (Boundary scanstandard, IEEE Std 1500) to apply the testing for 3D-VLSI. Next, wepoint out the issue of the testing for TSV in 3D-VLSI. Finally, weintroduce the test generation method for the faults at the TSVs.

Journal

Proceedings of JIEP Annual Meeting

Proceedings of JIEP Annual Meeting 28 (0), 231-234, 2014

The Japan Institute of Electronics Packaging

Details 詳細情報について

CRID: 1390845712979512192

NII Article ID: 130007429048

DOI: 10.11486/ejisso.28.0_231

Text Lang: ja

Data Source

JaLC
CiNii Articles

Abstract License Flag: Disallowed

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Survey of the testing for 3D-VLSI