A 1V 50MHz 15mW 32Kb SRAM using Malti Vth 0.35μm CMOS Technology
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- KAWASHIMA Shoichiro
- Fujitsu Laboratories Limited
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- WAKAYAMA Shigetoshi
- Fujitsu Laboratories Limited
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- SHIMAUCHI Yoshiki
- Fujitsu Laboratories Limited
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- SUKEGAWA Kazuo
- Fujitsu Limited
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- TSUBOI Osamu
- Fujitsu Limited
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- YAMAZAKI Tatsuya
- Fujitsu Limited
Bibliographic Information
- Other Title
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- マルチVth 0.35μm CMOSテクノロジ1V 50MHz 15mW 32Kb SRAM
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Description
A Split-Level-Latch Sense Amplifier (SLLS/A) using high Vth MOSs eliminates stable leakage current with only a 4 ns latching delay. A Super-VCC Gate voltage nMOS Load (SVGNL) bit-line load scheme combined with Bit-line Coupled Gate voltage Control (BCGC) produces a fast bit-line readout voltage swing and saves write operation current. These circuits together with a boosted pulsed word-line scheme realize a 14 ns macro access time and a 15 mA operation current at 1V power supply.
Journal
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- IEICE technical report. Electron devices
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IEICE technical report. Electron devices 96 (107), 27-34, 1996-06-20
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1570009752449371904
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- NII Article ID
- 110003200116
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- NII Book ID
- AN10012954
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
