Test Sequence Generation for Test Time Reduction of IDDQ Testing

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In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.

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詳細情報 詳細情報について

  • CRID
    1570009752557232384
  • NII論文ID
    110003213908
  • NII書誌ID
    AA10826272
  • ISSN
    09168532
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

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