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A Simple Determination Method for the Source and Drain Resistances in the Ultra-Short Schottky-Gate FETs
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- INOUE Takashi
- Kansai Electronics Research Laboratories, NEC Corporation
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- CONTRATA Walter
- Kansai Electronics Research Laboratories, NEC Corporation
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- OHATA Keiichi
- Kansai Electronics Research Laboratories, NEC Corporation
Bibliographic Information
- Other Title
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- 超微細ショットキー・ゲートFETのソース及びドレイン抵抗の簡易測定
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Description
A new method, "Vf method", is proposed to accurately evaluate the parasitic source and drain resistances (Rs, Rd) in Schottky-gate FETs using simple DC-measurements. The method is based on an improved gate-probing technique, which is effective even if a tested device gate has a relatively large ideality factor n larger than 1.2. And the method can evaluate the values of the Rs and Rd simply and accurately even if the device has an ultra-short gate-length Lg less than 0.15μm, because it applies a forward turn-on voltage (Vf) to the gate in order to reduce inhomogeneities in the gate current density characteristics (i.e. n-factor and apparent barrier height Φ_B) along the gate length.
Journal
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- IEICE technical report. Microwaves
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IEICE technical report. Microwaves 97 (288), 51-56, 1997-09-26
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1570291227453977344
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- NII Article ID
- 110003189248
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- NII Book ID
- AN10013185
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- Text Lang
- ja
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- Data Source
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- CiNii Articles