A 0.9ns-1.15Mb ECL-CMOS SRAM with 30ps-120k Gates

12 References

Bibliographic Information

Other Title
  • 30ps-120kゲート内蔵0.9ns-1.15Mb ECL-CMOS SRAM

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Description

A soft-error-immune 0.9ns 1.15Mb ECL-CMOS SRAM with 30-ps 120k logic gates has been developed. To provide good testability, reliability, and stability, on-chip test circuitry, a memory-cell test technique, a highly stable current source, and a soft-error-immune memory cell are proposed. To evaluate these new techniques, this new chip for cache SRAM of mainframe computer was fabricated using 0.3-um BiCMOS technology. This chip contributes in realizing high-performance mainframe computer.

Journal

  • Technical report of IEICE. SDM

    Technical report of IEICE. SDM 95 (379), 31-36, 1995-11-21

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1570291227512674688
  • NII Article ID
    110003309685
  • NII Book ID
    AN10013254
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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