Low-Power Multiple-Valued Current-Mode Logic Using Substrate Bias Control

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Abstract

A new multiple-valued current-mode (MVCM) logic circuit using substrate bias control is proposed for low-power VLSI systems at higher clock frequency. Since a multi-level threshold value is represented as a threshold voltage of an MOS transistor, a voltage comparator is realized by a single MOS transistor. As a result, two basic components, a comparator and an output generator in the MVCM logic circuit can be merged into a single MOS differential-pair circuit where the threshold voltages of MOS transistors are controlled by substrate biasing. Moreover, the leakage current is also reduced using substrate bias control. As a typical example of an arithmetic circuit, a radix-2 signed-digit full adder using the proposed circuit is implemented in a 0.18-μm CMOS technology. Its dynamic and static power dissipations are reduced to about 79 percent and 14 percent, respectively, in comparison with those of the corresponding binary CMOS implementation at the supply voltage of 1.8 V and the clock frequency of 500MHz.

Journal

  • IEICE Trans. Electron., C

    IEICE Trans. Electron., C 87 (4), 582-588, 2004-04-01

    The Institute of Electronics, Information and Communication Engineers

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Keywords

Details 詳細情報について

  • CRID
    1570291227535242112
  • NII Article ID
    110003214894
  • NII Book ID
    AA10826283
  • ISSN
    09168524
  • Text Lang
    en
  • Data Source
    • CiNii Articles

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