- 【Updated on May 12, 2025】 Integration of CiNii Dissertations and CiNii Books into CiNii Research
- Trial version of CiNii Research Knowledge Graph Search feature is available on CiNii Labs
- 【Updated on June 30, 2025】Suspension and deletion of data provided by Nikkei BP
- Regarding the recording of “Research Data” and “Evidence Data”
A-6-5 Evaluation of A Floorplan-aware High-level Synthesis Algorithm Optimizing Critical Path for FPGA Designs
-
- Fujiwara Koichi
- Department of Computer Science and Communications Engineering, Waseda University
-
- Kawamura Kazushi
- Department of Computer Science and Communications Engineering, Waseda University
-
- Yanagisawa Masao
- Department of Computer Science and Communications Engineering, Waseda University
-
- Togawa Nozomu
- Department of Computer Science and Communications Engineering, Waseda University
Bibliographic Information
- Other Title
-
- A-6-5 クリティカルパス最適化フロアプラン指向FPGA高位合成手法のアプリケーション適用評価(A-6.VLSI設計技術,一般セッション)
Search this article
Journal
-
- Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference
-
Proceedings of the IEICE Engineering Sciences Society/NOLTA Society Conference 2016 79-, 2016-03-01
The Institute of Electronics, Information and Communication Engineers
- Tweet
Details 詳細情報について
-
- CRID
- 1570291227542738304
-
- NII Article ID
- 110010023118
-
- NII Book ID
- AA12732012
-
- ISSN
- 2189700X
-
- Text Lang
- ja
-
- Data Source
-
- CiNii Articles