An analysis method of ADC sampling delay dependency on input signal using Verilog-A as a test bench

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Other Title
  • Verilog-A をテストベンチに用いたADコンバータのサンプリングディレイ入力依存性検証法

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Details 詳細情報について

  • CRID
    1570572700539935104
  • NII Article ID
    10019579784
  • NII Book ID
    AN10441815
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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