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Design and Implementation of Reconfigurable PCI card

  • ICHIKAWA Shuichi
    Dept. of Information Electronics, School of Engineering, Nagoya University
  • SHIMADA Toshio
    Dept. of Information Electronics, School of Engineering, Nagoya University

Bibliographic Information

Other Title
  • PCIバスに付加する再構成可能ボードの試作評価

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Abstract

Recent researches have shown that many application programs can be accelerated by implementing some part of software with reconfigurable devices, e.g. Field Programmable Gate Arrays. However, there are still many problems to apply this technique to personal computing applications. Cost limits available reconfigurable logic gates and standard bus restricts transfeT rate and latency. Quantitative measurem[ent is requiral to examine viability. In this paper, the design and implementation of FPGA logic card for PCI bus is reported, in which hardware is simplified to reduce cost and configuration time to serve small applications. Run-time reconfiguration can be performed in 1-10 ms for larger applications to reclaim reconfigurable logic gates. Two or more boards can be used in parallel. This board achieves 8-42MB/s in transfer rate and 0.33-0.45 μs in latency, under FreeBSD on 133 Mhz Pentium system.

Journal

  • Technical report of IEICE. VLD

    Technical report of IEICE. VLD 96 (425), 159-166, 1996-12-13

    The Institute of Electronics, Information and Communication Engineers

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References(17)*help

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Details

  • CRID
    1570572702385606656
  • NII Article ID
    110003294423
  • NII Book ID
    AN10013323
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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