Software Controled Cache for Multi-grain Parallel Processing

Bibliographic Information

Other Title
  • マルチグレイン並列処理を利用したソフトウェア制御キャッシュの開発

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Description

Multi-grain parallel processing is proposed so as to make the best use of inherent parallelism in sequential programs. Although this method can be implemented on various architecture, a dedicated architecture will exploit its maximum capacity. Multiprocessor system ASCA has been developed as such as architecture, and a software controlled cache for ASCA processor is designed here. Using the cache, most of miss-hit can be avoided by static schedulng, and if miss-scheduling is detected, it changes its mode into usual hardware controlled cache. From initial evaluation results, the performance is improved about 21% in comparison with the usual cache.

Journal

  • Technical report of IEICE. FTS

    Technical report of IEICE. FTS 98 (27), 117-124, 1998-04-24

    The Institute of Electronics, Information and Communication Engineers

Keywords

Details 詳細情報について

  • CRID
    1570572702399308160
  • NII Article ID
    110003194129
  • NII Book ID
    AN10012998
  • Text Lang
    ja
  • Data Source
    • CiNii Articles

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