A study of memory cell for high density DRAM
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- TADAKI Yoshitaka
- Hitachi, Devive development center
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- SEKIGUCHI Toshihiro
- Hitachi, Devive development center
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- MURATA Jun
- Hitachi, Devive development center
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- MURANAKA Masaya
- Hitachi VLSI engineering
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- MIURA Masashi
- Hitachi VLSI engineering
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- MAKABE Kazuya
- Hitachi VLSI engineering
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- KAERIYAMA Toshiyuki
- Texas Instruments Japan
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- CHO Songsu
- Texas Instruments Japan
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- YUHARA Katsuo
- Texas Instruments Japan
Bibliographic Information
- Other Title
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- 高集積DRAM構造の検討
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Description
Achieved high density DRAM adopting Gull-wing shape memory cell layout for active layer. Evaluation of isolation characteristics at electrically severe condition shows COPs cause isolation failures. Failure model is COP cause thinning of the oxide thickness of LOCOS.
Journal
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- Technical report of IEICE. SDM
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Technical report of IEICE. SDM 97 (240), 39-44, 1997-08-26
The Institute of Electronics, Information and Communication Engineers
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Details 詳細情報について
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- CRID
- 1570572702489172864
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- NII Article ID
- 110003309434
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- NII Book ID
- AN10013254
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- Text Lang
- ja
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- Data Source
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- CiNii Articles
