IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

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説明

In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.

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詳細情報 詳細情報について

  • CRID
    1570854177260582912
  • NII論文ID
    110006376583
  • NII書誌ID
    AA10826272
  • ISSN
    09168532
  • 本文言語コード
    en
  • データソース種別
    • CiNii Articles

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