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IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates
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- HASHIZUME Masaki
- Faculty of Engineering, The University of Tokushima
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- TAKEDA Teppei
- Faculty of Engineering, The University of Tokushima
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- ICHIMIYA Masahiro
- Faculty of Engineering, The University of Tokushima
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- YOTSUYANAGI Hiroyuki
- Faculty of Engineering, The University of Tokushima
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- MIURA Yukiya
- Graduate School of Engineering, Tokyo Metropolitan University
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- KINOSHITA Kozo
- Faculty of Informatics, Osaka Gakuin University
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Description
In this paper, a useful technique is proposed for realizing high speed IDDQ tests. By using the technique, load capacitors of the CMOS logic gates can be charged quickly, whose output logic values change from L to H by applying a test input vector to a circuit under test. The technique is applied to built-in I_<DDQ> sensor design and external I_<DDQ> sensor design. It is shown experimentally that high speed IDDQ tests can be realized by using the technique.
Journal
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- IEICE transactions on information and systems
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IEICE transactions on information and systems 85 (10), 1534-1541, 2002-10-01
The Institute of Electronics, Information and Communication Engineers
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Keywords
Details 詳細情報について
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- CRID
- 1570854177260582912
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- NII Article ID
- 110006376583
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- NII Book ID
- AA10826272
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- ISSN
- 09168532
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- Text Lang
- en
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- Data Source
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- CiNii Articles
